/**
  ******************************************************************************
  * @file    ys32md211_syscfg.c
  * @author  YSPRING Application Team
  * @version V1.0.1
  * @date    2025.02.15
  * @brief   This file provides firmware functions to manage the following 
  *          functionalities of the SYSCFG peripheral:
  *           + Remapping the memory mapped at 0x00000000  
  *           + Remapping the DMA channels
  *           + Configuring the TIMx break input(COMPx) 
  *           + Configuring the TIM1, TIM16 and TIM17 break input 
  *           + Configuring the TIM1_ETR input  
  *           + Select the ADC injection channel triggers remapping externally
  *   
  *  @verbatim
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..] 
               The SYSCFG registers can be accessed only when the SYSCFG 
               interface APB2 clock is enabled.
               To enable SYSCFG APB2 clock use:
               RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE).
  *  @endverbatim
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "ys32md211_syscfg.h"

/** @addtogroup YS32MD211_StdPeriph_Driver
  * @{
  */

/** @defgroup SYSCFG 
  * @brief SYSCFG driver modules
  * @{
  */ 

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/

/* ---------------------- SYSCFG registers bit mask ------------------------ */
#define CFGR2_COMPx_BRK_MASK             ((uint32_t)(SYSCFG_CFGR2_COMP2_BRK_TIM17 | SYSCFG_CFGR2_COMP1_BRK_TIM17 | \
                                                     SYSCFG_CFGR2_COMP2_BRK_TIM16 | SYSCFG_CFGR2_COMP1_BRK_TIM16 | \
                                                     SYSCFG_CFGR2_COMP2_BRK_TIM1  | SYSCFG_CFGR2_COMP1_BRK_TIM1))

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup SYSCFG_Private_Functions
  * @{
  */ 

/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
 *  @brief   SYSCFG Initialization and Configuration functions 
 *
@verbatim
 ===============================================================================
        ##### SYSCFG Initialization and Configuration functions #####
 ===============================================================================

@endverbatim
  * @{
  */

/**
  * @brief  Deinitializes the SYSCFG registers to their default reset values.
  * @param  None
  * @retval None
  * @note   MEM_MODE bits are not affected by APB reset.
  * @note   MEM_MODE bits took the value from the user option bytes.
  * @note   CFGR2 register is not affected by APB reset.
  * @note   CLABBB configuration bits are locked when set.
  * @note   To unlock the configuration, perform a system reset.
  */
void SYSCFG_DeInit(void)
{
  /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
  SYSCFG->CFGR1 &= (~SYSCFG_CFGR1_MEM_MODE);

  SYSCFG->CFGR2 = 0;
  SYSCFG->CFGR3 = 0;
  SYSCFG->CFGR4 = 0;

}

/**
  * @brief  Configures the memory mapping at address 0x00000000.
  * @param  SYSCFG_MemoryRemap: selects the memory remapping.
  *          This parameter can be one of the following values:
  *            @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
  *            @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
  *            @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
  * @param  MemoryRstMode: select whether SYSREQ reset is required.
  *          This parameter can be one of the following values:
  *            @arg SYSCFG_RST_SYSREQ: Need SYSREQ reset to take effect.
  *            @arg SYSCFG_RST_NOSYSREQ: Don't need SYSREQ reset and takes effect immediately.

  * @retval None
  */
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap, uint32_t MemoryRstMode)
{
  uint32_t tmpctrl = 0;

  /* Check the parameter */
  assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));

  /* Get CFGR1 register value */
  tmpctrl = SYSCFG->CFGR1;

  /* Clear MEM_MODE and REMAP_RST_SEL bits */
  tmpctrl &= (uint32_t) (~(SYSCFG_CFGR1_MEM_MODE | SYSCFG_CFGR1_REMAP_RST_SEL));

  /* Set the new MEM_MODE and REMAP_RST_SEL bits value */
  tmpctrl |= (uint32_t) (SYSCFG_MemoryRemap | MemoryRstMode);

  /* Set CFGR1 register with the new memory remap and memory reset mode configuration */
  SYSCFG->CFGR1 = tmpctrl;
}

/**
  * @brief  Configure the DMAx channels remapping.
  * @param  SYSCFG_DMAChannelx: x can be 1 to 3
  *         @arg SYSCFG_DMAChannel1: DMA Channel1 MAP 
  *         @arg SYSCFG_DMAChannel2: DMA Channel2 MAP 
  *         @arg SYSCFG_DMAChannel3: DMA Channel3 MAP 
  * @param  SYSCFG_DMARemap: 
  *         @arg SYSCFG_DMA_MAP_ADC       : DMA map to ADC       
  *         @arg SYSCFG_DMA_MAP_SPI1_TX   : DMA map to SPI1_TX   
  *         @arg SYSCFG_DMA_MAP_SPI1_RX   : DMA map to SPI1_RX    
  *         @arg SYSCFG_DMA_MAP_UART1_TX  : DMA map to UART1_TX  
  *         @arg SYSCFG_DMA_MAP_UART1_RX  : DMA map to UART1_RX  
  *         @arg SYSCFG_DMA_MAP_UART2_TX  : DMA map to UART2_TX  
  *         @arg SYSCFG_DMA_MAP_UART2_RX  : DMA map to UART2_RX  
  *         @arg SYSCFG_DMA_MAP_I2C1_TX   : DMA map to I2C1_TX   
  *         @arg SYSCFG_DMA_MAP_I2C1_RX   : DMA map to I2C1_RX    
  *         @arg SYSCFG_DMA_MAP_TIM1_CH1  : DMA map to TIM1_CH1  
  *         @arg SYSCFG_DMA_MAP_TIM1_CH2  : DMA map to TIM1_CH2  
  *         @arg SYSCFG_DMA_MAP_TIM1_CH3  : DMA map to TIM1_CH3  
  *         @arg SYSCFG_DMA_MAP_TIM1_CH4  : DMA map to TIM1_CH4  
  *         @arg SYSCFG_DMA_MAP_TIM1_COM  : DMA map to TIM1_COM  
  *         @arg SYSCFG_DMA_MAP_TIM1_UP   : DMA map to TIM1_UP   
  *         @arg SYSCFG_DMA_MAP_TIM1_TRIG : DMA map to TIM1_TRIG 
  *         @arg SYSCFG_DMA_MAP_TIM3_CH1  : DMA map to TIM3_CH1  
  *         @arg SYSCFG_DMA_MAP_TIM3_CH3  : DMA map to TIM3_CH3  
  *         @arg SYSCFG_DMA_MAP_TIM3_CH4  : DMA map to TIM3_CH4  
  *         @arg SYSCFG_DMA_MAP_TIM3_TRG  : DMA map to TIM3_TRG  
  *         @arg SYSCFG_DMA_MAP_TIM3_UP   : DMA map to TIM3_UP   
  *         @arg SYSCFG_DMA_MAP_TIM16_CH1 : DMA map to TIM16_CH1 
  *         @arg SYSCFG_DMA_MAP_TIM16_UP  : DMA map to TIM16_UP  
  *         @arg SYSCFG_DMA_MAP_TIM17_CH1 : DMA map to TIM17_CH1 
  *         @arg SYSCFG_DMA_MAP_TIM17_UP  : DMA map to TIM17_UP  
  * @param  NewState: new state of the DMA Channelx. 
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMAChannelx, uint32_t SYSCFG_DMARemap, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_SYSCFG_DMA_CHANNEL(SYSCFG_DMAChannelx));
  assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if(SYSCFG_DMAChannelx == SYSCFG_DMAChannel1)
  {
    SYSCFG->CFGR4 &= ~(0xFF<<SYSCFG_DMAChannelx*8);
    if (NewState != DISABLE)
    {
      SYSCFG->CFGR4 |= SYSCFG_DMARemap<<(SYSCFG_DMAChannelx*8);
      if(SYSCFG_DMARemap < SYSCFG_DMA_MAP_TIM1_CH1)
      {
        DMA_CHANNEL1 -> CCR |= DMA_CHANNEL_CCR_TRANS_MODE; //Set DMA CCR TRANS_MODE bit
      }
      else
      {
        DMA_CHANNEL1 -> CCR &= ~(DMA_CHANNEL_CCR_TRANS_MODE);//CLEAR DMA CCR TRANS_MODE bit
      }
    }  
  }

  else if(SYSCFG_DMAChannelx == SYSCFG_DMAChannel2)
  {
    SYSCFG->CFGR4 &= ~(0xFF<<SYSCFG_DMAChannelx*8);
    if (NewState != DISABLE)
    {
      SYSCFG->CFGR4 |= SYSCFG_DMARemap<<(SYSCFG_DMAChannelx*8);
      if(SYSCFG_DMARemap < SYSCFG_DMA_MAP_TIM1_CH1)
      {
        DMA_CHANNEL2 -> CCR |= DMA_CHANNEL_CCR_TRANS_MODE; //Set DMA CCR TRANS_MODE bit
      }
      else
      {
        DMA_CHANNEL2 -> CCR &= ~(DMA_CHANNEL_CCR_TRANS_MODE);//CLEAR DMA CCR TRANS_MODE bit
      }
    }  
  }

  else if(SYSCFG_DMAChannelx == SYSCFG_DMAChannel3)
  {
    SYSCFG->CFGR4 &= ~(0xFF<<SYSCFG_DMAChannelx*8);
    if (NewState != DISABLE)
    {
      SYSCFG->CFGR4 |= SYSCFG_DMARemap<<(SYSCFG_DMAChannelx*8);
      if(SYSCFG_DMARemap < SYSCFG_DMA_MAP_TIM1_CH1)
      {
        DMA_CHANNEL3 -> CCR |= DMA_CHANNEL_CCR_TRANS_MODE; //Set DMA CCR TRANS_MODE bit
      }
      else
      {
        DMA_CHANNEL3 -> CCR &= ~(DMA_CHANNEL_CCR_TRANS_MODE);//CLEAR DMA CCR TRANS_MODE bit
      }
    }  
  }
}

/**
  * @brief  ADC injection channel external trigger remapping selection.
  * @param  adc_remap: Select the timer channel to be connected.
  *         This parameter can be one of the following values:
  *            @arg SYSCFG_ADC_REMAP_TIM1_CC3_4: ADC injection conversion external trigger is connected to TIM1_CC3_CC4  
  *            @arg SYSCFG_ADC_REMAP_TIM1_CC2_3_4: ADC injection conversion external trigger is connected to TIM1_CC2_CC3_CC4  
  *            @arg SYSCFG_ADC_REMAP_TIM3_CC2_3_4: ADC injection conversion external trigger is connected to TIM3_CC2_CC3_CC4  
  *            @arg SYSCFG_ADC_REMAP_TIM3_CC1_2_3_4: ADC injection conversion external trigger is connected to TIM3_CC1_CC2_CC3_CC4  
  * @retval None
  */
void SYSCFG_ADCEtrInj_RemapSel(uint32_t adc_remap)
{
  uint32_t tmpremap = 0;

  /* Check the parameter */
  assert_param(IS_SYSCFG_ADC_ETRGINJ_REMAP(adc_remap));

  /* Get CFGR3 register value */
  tmpremap = SYSCFG->CFGR3;

  /* Clear ADC1_ETRGINJ_REMAP[1:0] bits */
  tmpremap &= (uint32_t) (~(SYSCFG_CFGR3_ADC1_ETRGINJ_REMAP_Msk));

  /* Set the new ADC1_ETRGINJ_REMAP[1:0] bits value */
  tmpremap |= (uint32_t) (adc_remap);

  /* Set CFGR3 register with the new ADC etrginj remap configuration */
  SYSCFG->CFGR3 = tmpremap;
}

/**
  * @brief  TIMER1 ETR Input source selection
  * @param  SYSCFG_ETR_TIM1: 
  *            @arg SYSCFG_ETR_TIM1_GPIO : ETR come from GPIO
  *            @arg SYSCFG_ETR_TIM1_COMP1: ETR come from COMP1
  *            @arg SYSCFG_ETR_TIM1_COMP2: ETR come from COMP2
  * @retval None
  */
void SYSCFG_COMP_ETR_TIM1(uint32_t SYSCFG_ETR_TIM1)
{
  assert_param(IS_SYSCFG_ETR_SRC_TIM1(SYSCFG_ETR_TIM1));

  SYSCFG->CFGR3 &= (~SYSCFG_CFGR3_ETR_SRC_TIM1);
  SYSCFG->CFGR3 |= SYSCFG_ETR_TIM1;
}

/**
  * @brief  COMPx As TIMx break Input enable
  * @param  SYSCFG_COMPX_TIMX: 
  *            @arg SYSCFG_COMP2_BREAK_TIM17: COMP2 output as TIM17 break input
  *            @arg SYSCFG_COMP1_BREAK_TIM17: COMP1 output as TIM17 break input
  *            @arg SYSCFG_COMP2_BREAK_TIM16: COMP2 output as TIM16 break input
  *            @arg SYSCFG_COMP1_BREAK_TIM16: COMP1 output as TIM16 break input
  *            @arg SYSCFG_COMP2_BREAK_TIM1 : COMP2 output as TIM1  break input
  *            @arg SYSCFG_COMP1_BREAK_TIM1 : COMP1 output as TIM1  break input
  * 
  * @retval None
  */
void SYSCFG_COMPx_Break(uint32_t SYSCFG_COMPx_TIMx)
{
  assert_param(IS_SYSCFG_COMPX_TIMX(SYSCFG_COMPx_TIMx));

  SYSCFG->CFGR2 &= (~CFGR2_COMPx_BRK_MASK);
  SYSCFG->CFGR2 |= SYSCFG_COMPx_TIMx;
}

/**
  * @brief  Connect the selected parameter to the break input of TIM1, TIM16 and TIM17.
  * @note   The selected configuration is locked and can be unlocked by system reset
  * @param  SYSCFG_Break: selects the configuration to be connected to break
  *         input of TIM1, TIM16 and TIM17.
  *         This parameter can be any combination of the following values:
  *            @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1
  *            @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
  * @retval None
  */
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
{
  /* Check the parameter */
  assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));

  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
}

/**
  * @}
  */

/**
  * @}
  */ 

/**
  * @}
  */ 

/**
  * @}
  */ 
