/**
  ******************************************************************************
  * @file    ys32md211_syscfg.h
  * @author  YSPRING Application Team
  * @version V1.0.1
  * @date    2025.02.15
  * @brief   This file contains all the functions prototypes for the SYSCFG firmware 
  *          library.
  ******************************************************************************
  */

/*!< Define to prevent recursive inclusion -------------------------------------*/
#ifndef __YS32MD211_SYSCFG_H
#define __YS32MD211_SYSCFG_H

#ifdef __cplusplus
 extern "C" {
#endif

/*!< Includes ------------------------------------------------------------------*/
#include "ys32md211.h"

/** @addtogroup YS32MD211_StdPeriph_Driver
  * @{
  */

/** @addtogroup SYSCFG
  * @{
  */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup SYSCFG_Exported_Constants
  * @{
  */ 

/** @defgroup SYSCFG_Memory_RST_Mode
* @{
*/
#define SYSCFG_RST_SYSREQ                       (0x00000000U)              
#define SYSCFG_RST_NOSYSREQ                     SYSCFG_CFGR1_REMAP_RST_SEL     
#define IS_SYSCFG_MEMORYRST_MODE(MODE) (((REMAP) == SYSCFG_RST_SYSREQ) || \
                                        ((REMAP) == SYSCFG_RST_NOSYSREQ))
/**
  * @}
  */

/** @defgroup SYSCFG_Memory_Remap_Config 
  * @{
  */ 
#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x03)
#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x01)


#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)        || \
                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))

/**
  * @}
  */

/** @defgroup SYSCFG_DMA_Remap_Config 
  * @{
  */ 
#define SYSCFG_DMAChannel1          0
#define SYSCFG_DMAChannel2          1  
#define SYSCFG_DMAChannel3          2  
#define IS_SYSCFG_DMA_CHANNEL(DMAChannel) (((DMAChannel) == SYSCFG_DMAChannel1) || \
                                           ((DMAChannel) == SYSCFG_DMAChannel2) || \
                                           ((DMAChannel) == SYSCFG_DMAChannel3))

#define        SYSCFG_DMA_MAP_ADC             0x00
#define        SYSCFG_DMA_MAP_SPI1_TX         0x01
#define        SYSCFG_DMA_MAP_SPI1_RX         0x02
#define        SYSCFG_DMA_MAP_UART1_TX        0x05
#define        SYSCFG_DMA_MAP_UART1_RX        0x06
#define        SYSCFG_DMA_MAP_UART2_TX        0x07
#define        SYSCFG_DMA_MAP_UART2_RX        0x08
#define        SYSCFG_DMA_MAP_I2C1_TX         0x0D
#define        SYSCFG_DMA_MAP_I2C1_RX         0x0E
#define        SYSCFG_DMA_MAP_TIM1_CH1        0x11
#define        SYSCFG_DMA_MAP_TIM1_CH2        0x12
#define        SYSCFG_DMA_MAP_TIM1_CH3        0x13
#define        SYSCFG_DMA_MAP_TIM1_CH4        0x14
#define        SYSCFG_DMA_MAP_TIM1_COM        0x15
#define        SYSCFG_DMA_MAP_TIM1_UP         0x16
#define        SYSCFG_DMA_MAP_TIM1_TRIG       0x17
#define        SYSCFG_DMA_MAP_TIM3_CH1        0x1E
#define        SYSCFG_DMA_MAP_TIM3_CH3        0x1F
#define        SYSCFG_DMA_MAP_TIM3_CH4        0x20
#define        SYSCFG_DMA_MAP_TIM3_TRG        0x21
#define        SYSCFG_DMA_MAP_TIM3_UP         0x22
#define        SYSCFG_DMA_MAP_TIM16_CH1       0x3E
#define        SYSCFG_DMA_MAP_TIM16_UP        0x3F
#define        SYSCFG_DMA_MAP_TIM17_CH1       0x40
#define        SYSCFG_DMA_MAP_TIM17_UP        0x41

#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMA_MAP_ADC)       || \
                                    ((REMAP) == SYSCFG_DMA_MAP_SPI_TX)    || \
                                    ((REMAP) == SYSCFG_DMA_MAP_SPI_RX)    || \
                                    ((REMAP) == SYSCFG_DMA_MAP_UART1_TX)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_UART1_RX)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_UART2_TX)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_UART2_RX)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_I2C_TX)    || \
                                    ((REMAP) == SYSCFG_DMA_MAP_I2C_RX)    || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_CH1)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_CH2)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_CH3)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_CH4)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_COM)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_UP)   || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM1_TRIG) || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM3_CH1)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM3_CH3)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM3_CH4)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM3_TRG)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM3_UP)   || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM16_CH1) || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM16_UP)  || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM17_CH1) || \
                                    ((REMAP) == SYSCFG_DMA_MAP_TIM17_UP))

/**
  * @}
  */

 /** @defgroup SYSCFG_ADC_ETRGINJ_REMAP 
  * @{
  */ 
#define SYSCFG_ADC_REMAP_TIM1_CC3_4             SYSCFG_CFGR3_ADC1_ETRGINJ_REMAP_00
#define SYSCFG_ADC_REMAP_TIM1_CC2_3_4           SYSCFG_CFGR3_ADC1_ETRGINJ_REMAP_01  
#define SYSCFG_ADC_REMAP_TIM3_CC2_3_4           SYSCFG_CFGR3_ADC1_ETRGINJ_REMAP_10  
#define SYSCFG_ADC_REMAP_TIM3_CC1_2_3_4         SYSCFG_CFGR3_ADC1_ETRGINJ_REMAP_11  
#define IS_SYSCFG_ADC_ETRGINJ_REMAP(REMAP_TIMx_CCx) (((REMAP_TIMx_CCx ) == SYSCFG_ADC_REMAP_TIM1_CC3_4)   || \
                                                     ((REMAP_TIMx_CCx ) == SYSCFG_ADC_REMAP_TIM1_CC2_3_4) || \
                                                     ((REMAP_TIMx_CCx ) == SYSCFG_ADC_REMAP_TIM3_CC2_3_4) || \
                                                     ((REMAP_TIMx_CCx ) == SYSCFG_ADC_REMAP_TIM3_CC1_2_3_4))
/**
  * @}
  */
  
 /** @defgroup SYSCFG_ETR_SRC_TIM1 
  * @{
  */ 
#define SYSCFG_ETR_TIM1_GPIO          SYSCFG_CFGR3_ETR_SRC_TIM1_ETR_SRC_GPIO
#define SYSCFG_ETR_TIM1_COMP1         SYSCFG_CFGR3_ETR_SRC_TIM1_ETR_SRC_COMP1  
#define SYSCFG_ETR_TIM1_COMP2         SYSCFG_CFGR3_ETR_SRC_TIM1_ETR_SRC_COMP2  
#define IS_SYSCFG_ETR_SRC_TIM1(COMP_ETR_TIM1 ) (((COMP_ETR_TIM1 ) == SYSCFG_ETR_TIM1_GPIO)  || \
                                                 ((COMP_ETR_TIM1 ) == SYSCFG_ETR_TIM1_COMP1) || \
                                                 ((COMP_ETR_TIM1 ) == SYSCFG_ETR_TIM1_COMP2))
/**
  * @}
  */

/** @defgroup SYSCFG_BRK_TIMX 
  * @{
  */ 
#define  SYSCFG_COMP2_BREAK_TIM17  SYSCFG_CFGR2_COMP2_BRK_TIM17
#define  SYSCFG_COMP1_BREAK_TIM17  SYSCFG_CFGR2_COMP1_BRK_TIM17
#define  SYSCFG_COMP2_BREAK_TIM16  SYSCFG_CFGR2_COMP2_BRK_TIM16
#define  SYSCFG_COMP1_BREAK_TIM16  SYSCFG_CFGR2_COMP1_BRK_TIM16
#define  SYSCFG_COMP2_BREAK_TIM1   SYSCFG_CFGR2_COMP2_BRK_TIM1 
#define  SYSCFG_COMP1_BREAK_TIM1   SYSCFG_CFGR2_COMP1_BRK_TIM1 
#define IS_SYSCFG_COMPX_TIMX(COMPx_TIMx) (((COMPx_TIMx ) == SYSCFG_COMP2_BREAK_TIM17) || \
                                          ((COMPx_TIMx ) == SYSCFG_COMP1_BREAK_TIM17) || \
                                          ((COMPx_TIMx ) == SYSCFG_COMP2_BREAK_TIM16) || \
                                          ((COMPx_TIMx ) == SYSCFG_COMP1_BREAK_TIM16) || \
                                          ((COMPx_TIMx ) == SYSCFG_COMP2_BREAK_TIM1 ) || \
                                          ((COMPx_TIMx ) == SYSCFG_COMP1_BREAK_TIM1 ))
/**                                                    
  * @}
  */

/** @defgroup SYSCFG_Lock_Config 
  * @{
  */ 
#define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK       /*!< Connects the PVD event to the Break Input of TIM1, not available for YS32MD211 devices */
#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */

#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
                                       ((CONFIG) == SYSCFG_Break_Lockup))

/**
  * @}
  */

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/*  Function used to set the SYSCFG configuration to the default reset state **/
void SYSCFG_DeInit(void);

/* SYSCFG configuration functions *********************************************/ 
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap, uint32_t MemoryRstMode);
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMAChannelx, uint32_t SYSCFG_DMARemap, FunctionalState NewState);
void SYSCFG_COMP_ETR_TIM1(uint32_t SYSCFG_ETR_TIM1);
void SYSCFG_COMPx_Break(uint32_t SYSCFG_COMPX_TIMX);
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);

#ifdef __cplusplus
}
#endif

#endif /*__YS32MD211_SYSCFG_H */

/**
  * @}
  */ 

/**
  * @}
  */ 

